About this opportunity:

The master thesis background can focus on the optimization and performance improvement aspects of network-on-chip (NoC) architecture. It can delve into the challenges and limitations associated with current NIC architecture and explore the potential benefits of transitioning to NI-700 based architecture. The thesis can aim to address the need for flexible performance path definition, avoidance of deadlock, enhancement of system throughput, and simplification of address STA violations. The research can also emphasize the significance of discussing configuration parameters at the project’s outset and their ownership by system architects for optimal performance.

What you will do:

The objective of the master thesis could be to evaluate and analyze the potential benefits and feasibility of transitioning from the current NIC architecture to the NI-700 based architecture in the context of network-on-chip (NoC) design. The scope of the thesis would include investigating how the NI-700 architecture addresses and resolves the limitations of the existing NIC architecture, particularly in terms of avoiding deadlock, supporting higher throughput requirements, and simplifying address STA violations. The thesis would also aim to assess the impact of transitioning to NI-700 architecture on the flexibility of performance path definition and the workload of the integration team. Additionally, the objective would be to explore the potential for achieving optimal AXI path control and system performance through early configuration parameter discussions and ownership by system architects.

The skills you bring:

– Students of computer science, computer engineering, or similar program

– Knowledge of RTL Design

– Interest in ASIC and SystemVerilog