Master Thesis: Automatic memory allocation

Join our Team
With the introduction of the 5G and 6G networks, we have and will see increasing need of compute resources. One part of that is that more processing will be done in dedicated hardware accelerators or in application specific processors. Many of these processing entities will have their own local data memory.

The focus of this master thesis is to suggest a memory allocation/deallocation algorithm and try it out in real hardware implementation.

What you will do:
This master thesis work is about investigating how to implement a memory allocator/deallocator in hardware and to investigate the trade-offs between speed/size versus the utilization of the memory. To do this, we suggest an approach where the work includes:

• Investigate and suggest a memory allocation/deallocation algorithm,
• Investigate latency, throughput, fragmentation and memory utilization for the chosen algorithm,
• Implement a reference model in Julia (or other simulation tools) to test and verify the design choices as well as to compare with other solutions,
• Design a hardware unit for the chosen memory allocator/deallocator,

We are searching for two students that are focused, creative, and knowledgeable in memory management, hardware design and programing. Preferably the students should have some experience in RTL (VHDL or SystemVerilog), and Julia (or similar simulation framework).

Why join Ericsson?
At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.