What you will do:

The following steps are envisioned as part of the thesis work:

• Perform a literature survey to gain familiarity with digital filtering architectures including pros and cons of the respective versions suitable for the specific use-case.
• Develop methods and a framework for optimizing the selected set of filter architectures for different specifications including, e.g., finite coefficients and data word lengths.
• Design a set of filters with different architectures for one filter configuration using the developed design framework and then extending the single filter configuration framework to multi-configuration optimization.
• Map the optimized filter structures to digital implementations in Verilog code and compare the resulting area and power consumption figures with the existing reference design

The thesis will be concluded with a result presentation for the Ericsson team.

The skills you bring:

• This project aims at students in electrical engineering, computer engineering or similar with an interest in digital IC design.
• Understanding of optimization and filter design
• Experience with digital IC tools and Verilog coding

Extent: 1-2 students, 30hp each

Location: Ericsson AB Mjärdevi, Linköping

Preferred Starting Date: January 2025

Applications should include a CV, transcript, and cover letter. Candidates are encouraged to submit their application as soon as possible.